Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

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Figure 8 from Air spacer for 10nm FinFET CMOS and beyond

sdavis Siliconica

Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

Integration SpringerLink

Scaling aligned carbon nanotube transistors to a sub-10 nm node

November, 2016

Figure 3 from FinFET With Encased Air-Gap Spacers for High

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Siliconica Just another Solid State Technology Sites site

Siliconica Just another Solid State Technology Sites site

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era - ScienceDirect

Siliconica Just another Solid State Technology Sites site

DTCO flow for air spacer generation and its impact on power and

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